Leakage power is one of the key challenges faced by the semiconductor device industry today. Sub-threshold leakage current is the dominant cause for leakage power at 130-nm and below and this trend is expected to continue in the future, especially since both the number of devices on a chip and leakage current of each device are increasing steadily. Leakage power optimization techniques can be divided into two groups, those addressing “standby leakage”, and “runtime leakage”. The former uses techniques like use of sleep transistors, transistor stacking, input vector control, etc. that reduce the leakage current when the block/cells are idle. The latter uses techniques that reduce the threshold voltage for cells statically (at design time) or dynamically (at runtime).
Reducing the threshold voltage improves speed significantly but makes devices leakier. On the other hand, using high threshold voltage devices makes circuits operate slower but leak less. Given that the technology trend is to lower threshold voltages, designers often use high-speed gates on the critical path(s) and high threshold voltage gates on the non-critical paths. The use of gates with different threshold voltages is achieved by using extra masks and lithography steps during fabrication, which increase manufacturing cost.
As a consequence, there is a need for a method of designing semiconductor device chips with reduced power consumption.